Programmable logic devices (PLDs) (e.g., field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), field programmable systems on a chip (FPSCs), or other types of programmable devices) may be configured with various user designs to implement desired functionality. Typically, the user designs are synthesized and mapped into configurable resources (e.g., programmable logic gates, look-up tables (LUTs), embedded hardware, or other types of resources) and interconnections available in particular PLDs. Physical placement and routing for the synthesized and mapped user designs may then be determined to generate configuration data for the particular PLDs.
User designs for PLDs can include one or more multiplexer structures configured to selectively forward one of a plurality of input signals (e.g., a “multiplexer” or “mux” multiplexer structure) or to selectively distribute one input signal across a plurality of outputs (e.g., a “demultiplexer” or “demux” multiplexer structure). Conventional methods for synthesizing and/or mapping multiplexer structures often allocate configurable resources and interconnections in a PLD inefficiently, which can unnecessarily limit the scope of available user designs for a particular size or capability of PLD.
Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.